PCIe® 6.0: Testing for a New Generation

PCIe 6.0 test solutions

Get this PDF emailed to you.

All information that you supply is protected by our privacy policy. By submitting your information you agree to our Terms of Use.

This white paper from Anritsu outlines the enhanced PCIe 6.0 technologies, such as PAM4, Forward Error Correction (FEC) and link equalization. It also provides guidelines on selecting the proper test system to verify PCIe 6.0 designs.

More

PCI-SIG is developing PCI Express (PCIe) 6.0 to meet the high-speed data transmission needs of emerging applications. With the doubling of data rates and other enhanced performance specifications, the new standard will add complexity and create design challenges for high-speed interconnect designs. Slated for finalization in 2021, engineers should already be integrating it into their design plans. But, engineers need to select the proper signal integrity test solutions to verify that their products are compliant with the new standards.

This white paper from Anritsu outlines the enhanced PCIe 6.0 technologies, such as 32 Gbaud PAM4 signaling, Forward Error Correction (FEC) and link equalization. It also provides guidelines on selecting the proper test system to verify PCIe 6.0 designs, which includes a protocol-aware bit error rate tester (BERT) and an oscilloscope. With a sound testing process, producers of data center products and systems will be able to have a greater confidence in their complex designs for emerging applications.